The present invention, in some embodiments thereof, relates to an electric nanodevice and its fabrication and, more particularly, but not exclusively, to a vertical transistor device having a nanometric channel.
Integrated circuits, such as ultra-large-scale integrated circuits, can include as many as one million transistors or more. The circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs), each including semiconductor gates adjacent a channel region and between drain and source regions. The drain and source regions are typically heavily doped with a p-type or an n-type dopant.
Generally, conventional integrated circuits have employed lateral transistors or devices. Lateral transistors include source and drain regions disposed below a top surface of a bulk or semiconductor-on-insulator (SOI) substrate and a gate disposed above the top surface. Thus, the source region, drain region, and gate of lateral transistors each consumes valuable space on the top surface of the substrate. The gate is disposed on only one side of a channel between the source and the drain. Accordingly, the conventional lateral device can have a limited drive current.
As demands for integration (transistor density) increase, vertical transistors have been considered. Vertical transistors can be insulated gate field effect transistors (IGFETs), such as, MOSFETS. In a conventional vertical MOSFET, source and drain regions are provided on opposite surfaces (e.g., a top surface and a bottom surface) of a semiconductor layer and a body region is disposed between the source and drain regions. During MOSFET operation, current flows vertically between the source and drain regions through a channel within the body region. The channel is often described in terms of its length, which is commonly defined as the spacing between the source and drain regions at the semiconductor surface, and its width, which is commonly defined as the dimension perpendicular to the length. In vertical transistors, the channel width is typically far greater than channel length.
Numerous techniques have been developed for the fabrication of semiconductor vertical transistors. Representative examples include Stutzmann, et al., Science 2003, 299, 1881-1884; Schmidt et al., Small 2006, 2, 85-88; Lee et al., Nano Lett 2003, 3, 113-117; Kagan et al., Nano Letters 2003 Vol. 3 No. 2 pp 119-124; and Maruccio et al. Adv Mater 2005, 17, 816.822.
Additional background art includes U.S. Pat. Nos. 6,180,956, 6,855,977; U.S. Published Application Nos. 20020175390, 20050032203, 20050040417, 20050151261, 20050189536, 20070102699, 20070145371, 20070181871, 20070210313; and International Patent Publication Nos. WO/03052835 and WO/07004803.